Phase Change Memory (PCM) is a promising candidate for next-generation main memory due to its low power consumption, but its endurance has limited its further application. The existed DRAM buffering and wear-leveling technologies were proposed to overcome the PCM endurance problem from two design issues:write count reduction and uniform write count distribution. However, the former fails to consider the access tendency when writing back pages. The latter can be further enhanced in terms of operation granularity, space overhead, and random access, especially in data streams of strong spatial locality. Therefore, the authors designed a novel hybrid memory architecture based on DRAM and PCM, proposed a replacement policy according to LRU (Least Recently Used) and LFU-Aging (Least Frequenctly Used with Aging) for the prediction of read and write access tendency, and finally presented a Bloom Filter (BF) based dynamic wear-leveling algorithm for strong-locality applications. The scheme can effectively decrease redundant write operations and realize inter-group wear-leveling with low space-overhead. The experimental results indicate that our scheme can reduce 13.4%-38.6% write operations in PCM and effectively homogenize the distribution of write counts for up to 90% groups.